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Designs need efficient floor plans at 45 nm
With the move to the 45-nanometer process node, more chip designs are going to be pad-limited, and die sizes will be directly affected by how efficiently I/Os are placed and sequenced. Details... more...
Minimizing layout hot spots at the 45-nm node
As technology migrates from 90 nm to 65 nm and, eventually, to the 45-nm node, fast yield ramp-up is increasingly difficult to achieve due to the sub-wavelength effects of lithography. Details... more...
Connect the dots
The problem with asset lite and foundries Details... more...