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Jitter peaking and PLLs
Jitter peaking with each PLL degrades the timing of the input signal. As this signal passes through subsequent PLLs, jitter peaking can accumulate to cause instability or timing failures. Details... more...
PCB prototypes add value in the design process
I would have guessed that most designers ordering prototype PCBs would not order the PCB in the target-system form factor. Details... more...
VHDL program enables PCI-bus-arbiter core
A simple VHDL program enables microprocessors or DSPs to act as PCI-bus masters. Details... more...