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Although methodologies for power network synthesis typically assume that design tools can freely size sleep transistors for power gating, this assumption does not hold up for real-world SoC designs where the sleep transistors are commonly designed as custom switch cells of fixed sizes. The method described in this article avoids this unrealistic assumption and introduces the concept of a "fake via" to enable power network synthesis using existing EDA tools. Details... more...

Microchip Expands Small PIC(r) MCUs w/ 20-Pin Family & More Capabilities Details... more...

C&K Compo 5b4 nents has developed a variety of detect switches for use in ATCA applications. These detect switches serve as a safety mechanism in server blades. Details... more...