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Analyze simultaneous switching noise in PCBs
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Analyze simultaneous switching noise in PCBs |
This article from Altera offers a systematic SSN overview with the focus on SSN caused by FPGA output buffers. A description of the causes of system-level SSO is presented and a hierarchical system-level SSO modeling methodology is proposed. A procedure for correlating the SSO models to frequency- and time-domain measurements is provided and several PCB design methodologies for minimizing SSO in PCBs are offered.
Details
2007-12-17 00:00:00
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